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| author | Tim Corringham <tcorring@amd.com> | 2020-06-19 18:23:56 +0100 |
|---|---|---|
| committer | Tim Corringham <tcorring@amd.com> | 2020-06-24 14:11:29 +0100 |
| commit | c3b3b999ec9ef7e8d9367848db82c97a0369473f (patch) | |
| tree | 2e6c96eb6f3c4a111a2b6e60867292d54f929fb4 /llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp | |
| parent | ab27603c6d444b15e5f8efc090611488440211a9 (diff) | |
| download | llvm-c3b3b999ec9ef7e8d9367848db82c97a0369473f.zip llvm-c3b3b999ec9ef7e8d9367848db82c97a0369473f.tar.gz llvm-c3b3b999ec9ef7e8d9367848db82c97a0369473f.tar.bz2 | |
[AMDGPU] Avoid redundant mode register writes
Summary:
The SIModeRegister pass attempts to generate the minimal number of
writes to the mode register. However it was failing to correctly
deal with some loops, resulting in some redundant setreg instructions
being inserted.
This change amends the pass to avoid generating these redundant
instructions.
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D82215
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp')
0 files changed, 0 insertions, 0 deletions