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authorYongKang Zhu <yongzhu@fb.com>2025-09-25 13:18:57 -0700
committerGitHub <noreply@github.com>2025-09-25 13:18:57 -0700
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parent185ae5cdc695248b58ae017508cc764c19bee5b7 (diff)
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[BOLT][AArch64][instr] Consider targeting ARM64 CPUs without LSE support (#158738)
`stadd` is only available in recent arm64 CPUs that have LSE support (like Cortex-A73 and Cortex-A75) and is not available on old arm64 CPUs (like Cortex-A53 and Cortex-A55). Devices could have a mixture of these two kinds of CPUs, for which we need to provide an option for BOLT to generate instrumentation sequence that emulates what `stadd` would do. The implementation puts counter increment into an injected helper function so we don't need to update CFG in the function that is being instrumented and instrumentation induced binary size increase will be smaller.
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