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| author | Hsiangkai Wang <kai.wang@sifive.com> | 2021-01-15 11:27:11 +0800 |
|---|---|---|
| committer | Hsiangkai Wang <kai.wang@sifive.com> | 2021-01-16 23:21:29 +0800 |
| commit | 098dbf190a5586d02f48b84eb41b93b701cdeb97 (patch) | |
| tree | 2d5ab44aadd0c699af6827b27a316532f42201a0 /llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp | |
| parent | a4e2a5145a29af678139f33e94ab3df0fc973e59 (diff) | |
| download | llvm-098dbf190a5586d02f48b84eb41b93b701cdeb97.zip llvm-098dbf190a5586d02f48b84eb41b93b701cdeb97.tar.gz llvm-098dbf190a5586d02f48b84eb41b93b701cdeb97.tar.bz2 | |
[RISCV] Correct alignment settings for vector registers.
According to "9. Vector Memory Alignment Constraints" in V
specification, the alignment of vector memory access is aligned to the
size of the element. In our current implementation, we support ELEN up
to 64. We could assume the alignment of vector registers is 64 under the
assumption.
Differential Revision: https://reviews.llvm.org/D94751
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp')
0 files changed, 0 insertions, 0 deletions