diff options
| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-09-23 19:16:01 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-09-23 19:16:01 +0000 |
| commit | 9202c9fb478bf5889728ebd32557e2f221a21726 (patch) | |
| tree | 973fb7aa5be1f28741b23d9972a9b26575d83b11 /llvm/lib/Target/WebAssembly/WebAssemblyFixFunctionBitcasts.cpp | |
| parent | b3478fcf0e54405377aebe6cb323f5c347e2f8e6 (diff) | |
| download | llvm-9202c9fb478bf5889728ebd32557e2f221a21726.zip llvm-9202c9fb478bf5889728ebd32557e2f221a21726.tar.gz llvm-9202c9fb478bf5889728ebd32557e2f221a21726.tar.bz2 | |
[X86] ROR*mCL instruction models should match ROL*mCL etc.
Confirmed with Craig Topper - fix a typo that was missing a Port4 uop for ROR*mCL instructions on some Intel models.
Yet another step on the scheduler model cleanup marathon......
llvm-svn: 342846
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyFixFunctionBitcasts.cpp')
0 files changed, 0 insertions, 0 deletions