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authorAlexis Engelke <engelke@in.tum.de>2024-08-04 18:34:26 +0200
committerGitHub <noreply@github.com>2024-08-04 18:34:26 +0200
commitda0e66e64c39bf43d143ef271c301e49a5a5d2f4 (patch)
treec0362229df6dab97740cf4d0640acf914cbef0dd /llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
parent7df9da7d780f1ece175020c5aef44b4b06df05b7 (diff)
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[CodeGen][NFC] Add wrapper method for MBBMap (#101893)
This is a preparation for changing the data structure of MBBMap.
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp')
-rw-r--r--llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp8
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
index ea795cd..317c646 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
@@ -220,7 +220,7 @@ bool WebAssemblyFastISel::computeAddress(const Value *Obj, Address &Addr) {
// Don't walk into other basic blocks unless the object is an alloca from
// another block, otherwise it may not have a virtual register assigned.
if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
- FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
+ FuncInfo.getMBB(I->getParent()) == FuncInfo.MBB) {
Opcode = I->getOpcode();
U = I;
}
@@ -1309,13 +1309,13 @@ bool WebAssemblyFastISel::selectStore(const Instruction *I) {
bool WebAssemblyFastISel::selectBr(const Instruction *I) {
const auto *Br = cast<BranchInst>(I);
if (Br->isUnconditional()) {
- MachineBasicBlock *MSucc = FuncInfo.MBBMap[Br->getSuccessor(0)];
+ MachineBasicBlock *MSucc = FuncInfo.getMBB(Br->getSuccessor(0));
fastEmitBranch(MSucc, Br->getDebugLoc());
return true;
}
- MachineBasicBlock *TBB = FuncInfo.MBBMap[Br->getSuccessor(0)];
- MachineBasicBlock *FBB = FuncInfo.MBBMap[Br->getSuccessor(1)];
+ MachineBasicBlock *TBB = FuncInfo.getMBB(Br->getSuccessor(0));
+ MachineBasicBlock *FBB = FuncInfo.getMBB(Br->getSuccessor(1));
bool Not;
unsigned CondReg = getRegForI1Value(Br->getCondition(), Br->getParent(), Not);