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| author | Pierre-vh <pierre.vanhoutryve@arm.com> | 2020-04-07 15:09:56 +0100 |
|---|---|---|
| committer | Pierre-vh <pierre.vanhoutryve@arm.com> | 2020-05-05 10:03:02 +0100 |
| commit | ffdda495f79a3147c4b351b323235ec429cc4f7d (patch) | |
| tree | 28a786d44546846671e541f2713a5a19d9a63be9 /llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp | |
| parent | 48aebfc908ba7b9372aaa478a9c200789491096e (diff) | |
| download | llvm-ffdda495f79a3147c4b351b323235ec429cc4f7d.zip llvm-ffdda495f79a3147c4b351b323235ec429cc4f7d.tar.gz llvm-ffdda495f79a3147c4b351b323235ec429cc4f7d.tar.bz2 | |
[Target][ARM] Add PerformVSELECTCombine for MVE Integer Ops
This patch adds an implementation of PerformVSELECTCombine in the
ARM DAG Combiner that transforms vselect(not(cond), lhs, rhs) into
vselect(cond, rhs, lhs).
Normally, this should be done by the target-independent DAG Combiner,
but it doesn't handle the kind of constants that we generate, so we
have to reimplement it here.
Differential Revision: https://reviews.llvm.org/D77712
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp')
0 files changed, 0 insertions, 0 deletions