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| author | Craig Topper <craig.topper@intel.com> | 2019-02-08 00:44:39 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-02-08 00:44:39 +0000 |
| commit | c782f188356426e2dce848d41d4155687adefac2 (patch) | |
| tree | 57412dc18fd290f9aa007a5a020bd0c1e7ed8195 /llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp | |
| parent | 28e967aaa1ecc6ff9b22f64c6057f56abe5503b8 (diff) | |
| download | llvm-c782f188356426e2dce848d41d4155687adefac2.zip llvm-c782f188356426e2dce848d41d4155687adefac2.tar.gz llvm-c782f188356426e2dce848d41d4155687adefac2.tar.bz2 | |
[X86] Add FPCW as a register and start using it as an implicit use on floating point instructions.
Summary:
FPCW contains the rounding mode control which we manipulate to implement fp to integer conversion by changing the roudning mode, storing the value to the stack, and then changing the rounding mode back. Because we didn't model FPCW and its dependency chain, other instructions could be scheduled into the middle of the sequence.
This patch introduces the register and adds it as an implciit def of FLDCW and implicit use of the FP binary arithmetic instructions and store instructions. There are more instructions that need to be updated, but this is a good start. I believe this fixes at least the reduced test case from PR40529.
Reviewers: RKSimon, spatel, rnk, efriedma, andrew.w.kaylor
Subscribers: dim, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D57735
llvm-svn: 353489
Diffstat (limited to 'llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions