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| author | Craig Topper <craig.topper@sifive.com> | 2025-04-17 12:39:40 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-04-17 12:39:40 -0700 |
| commit | b30100b87f24847afd6407b4939a184ebcf16ef9 (patch) | |
| tree | 6aeb24223f86343fa5cb71a3dbe7b3e0bffbed09 /llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp | |
| parent | 85110ccee90380a9d2bc930fae8fb0fa395d58d6 (diff) | |
| download | llvm-b30100b87f24847afd6407b4939a184ebcf16ef9.zip llvm-b30100b87f24847afd6407b4939a184ebcf16ef9.tar.gz llvm-b30100b87f24847afd6407b4939a184ebcf16ef9.tar.bz2 | |
[RISCV] Check that both registers of a CV Reg-Reg memory address are GPRs. (#136079)
The assembly parser was checking for any register instead of GPR.
I've removed the custom diagnostic message from the RegReg operand to
give a less confusing error on bad input. The mnemonics are shared with
other encodings that don't use reg-reg memory operand.
I also fixed the parsed operand location, but I'm not sure it matters.
Diffstat (limited to 'llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions