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| author | Craig Topper <craig.topper@sifive.com> | 2025-04-08 17:53:39 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-04-08 17:53:39 -0700 |
| commit | 9a762bb4e17969e69e4d1ce383fd0ccd41fb8e2e (patch) | |
| tree | 31993aa1e64a93c6723c0269936ddfbe0f9ae634 /llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp | |
| parent | ccf22848da9f050e00f23c5d4bc412ab19e81645 (diff) | |
| download | llvm-9a762bb4e17969e69e4d1ce383fd0ccd41fb8e2e.zip llvm-9a762bb4e17969e69e4d1ce383fd0ccd41fb8e2e.tar.gz llvm-9a762bb4e17969e69e4d1ce383fd0ccd41fb8e2e.tar.bz2 | |
[RISCV] Reuse existing tablegen classes for Zilsd/Zclsd. NFC (#134946)
We don't need pair specific classes. We just need to pass the pair
RegisterOperand to the existing classes we use for the base ISA and Zca.
For Zclsd, we need to changes the classes to take DAGOperand instead of
RegisterClass so we can pass a RegisterOperand.
Diffstat (limited to 'llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions