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| author | Pengcheng Wang <wangpengcheng.pp@bytedance.com> | 2024-11-15 17:53:14 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-15 17:53:14 +0800 |
| commit | 9122c5235ec85ce0c0ad337e862b006e7b349d84 (patch) | |
| tree | 90e754222effe3830e7bc9eb54ed178cab174816 /llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp | |
| parent | 5bbe63ec91226c0026c6f1ed726c45bb117544e0 (diff) | |
| download | llvm-9122c5235ec85ce0c0ad337e862b006e7b349d84.zip llvm-9122c5235ec85ce0c0ad337e862b006e7b349d84.tar.gz llvm-9122c5235ec85ce0c0ad337e862b006e7b349d84.tar.bz2 | |
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
This is based on other targets like PPC/AArch64 and some experiments.
This PR will only enable bidirectional scheduling and tracking register
pressure.
Disclaimer: I haven't tested it on many cores, maybe we should make
some options being features. I believe downstreams must have tried
this before, so feedbacks are welcome.
Diffstat (limited to 'llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions