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| author | hev <wangrui@loongson.cn> | 2023-10-11 10:24:18 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-10-11 10:24:18 +0800 |
| commit | 203ba238e33c570dba6cbcf247f1668bb2a13c26 (patch) | |
| tree | 79d507aca3588eb5a0bd56d846cda7b524f27318 /llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp | |
| parent | a157e79dd207d72aea1d42953c61f14790d847c1 (diff) | |
| download | llvm-203ba238e33c570dba6cbcf247f1668bb2a13c26.zip llvm-203ba238e33c570dba6cbcf247f1668bb2a13c26.tar.gz llvm-203ba238e33c570dba6cbcf247f1668bb2a13c26.tar.bz2 | |
[LoongArch] Improve codegen for atomic ops (#67391)
This PR improves memory barriers generated by atomic operations.
Memory barrier semantics of LL/SC:
```
LL: <memory-barrier> + <load-exclusive>
SC: <store-conditional> + <memory-barrier>
```
Changes:
* Remove unnecessary memory barriers before LL and between LL/SC.
* Fix acquire semantics. (If the SC instruction is not executed, then
the guarantee of acquiring semantics cannot be ensured. Therefore, an
acquire barrier needs to be generated when memory ordering includes an
acquire operation.)
Diffstat (limited to 'llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions