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| author | Evan Cheng <evan.cheng@apple.com> | 2011-07-20 07:51:56 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2011-07-20 07:51:56 +0000 |
| commit | efd9b4240f78a632b7e46697a94db6c74d2487b9 (patch) | |
| tree | 32a97747ae79f5b6d584f499cbdc4e35c13b41ec /llvm/lib/Target/Sparc/SparcTargetMachine.cpp | |
| parent | d2b92d6544c06d8a7af6939a587b781ca1d37342 (diff) | |
| download | llvm-efd9b4240f78a632b7e46697a94db6c74d2487b9.zip llvm-efd9b4240f78a632b7e46697a94db6c74d2487b9.tar.gz llvm-efd9b4240f78a632b7e46697a94db6c74d2487b9.tar.bz2 | |
- Move CodeModel from a TargetMachine global option to MCCodeGenInfo.
- Introduce JITDefault code model. This tells targets to set different default
code model for JIT. This eliminates the ugly hack in TargetMachine where
code model is changed after construction.
llvm-svn: 135580
Diffstat (limited to 'llvm/lib/Target/Sparc/SparcTargetMachine.cpp')
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcTargetMachine.cpp | 21 |
1 files changed, 11 insertions, 10 deletions
diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp index 218c4bc..c6b4e44 100644 --- a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp @@ -26,8 +26,9 @@ extern "C" void LLVMInitializeSparcTarget() { /// SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM, bool is64bit) - : LLVMTargetMachine(T, TT, CPU, FS, RM), + Reloc::Model RM, CodeModel::Model CM, + bool is64bit) + : LLVMTargetMachine(T, TT, CPU, FS, RM, CM), Subtarget(TT, CPU, FS, is64bit), DataLayout(Subtarget.getDataLayout()), TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget), @@ -51,15 +52,15 @@ bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM, } SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, - StringRef TT, - StringRef CPU, - StringRef FS, Reloc::Model RM) - : SparcTargetMachine(T, TT, CPU, FS, RM, false) { + StringRef TT, StringRef CPU, + StringRef FS, Reloc::Model RM, + CodeModel::Model CM) + : SparcTargetMachine(T, TT, CPU, FS, RM, CM, false) { } SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, - StringRef TT, - StringRef CPU, - StringRef FS, Reloc::Model RM) - : SparcTargetMachine(T, TT, CPU, FS, RM, true) { + StringRef TT, StringRef CPU, + StringRef FS, Reloc::Model RM, + CodeModel::Model CM) + : SparcTargetMachine(T, TT, CPU, FS, RM, CM, true) { } |