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| author | Joe Nash <Joseph.Nash@amd.com> | 2022-04-27 09:17:25 -0400 |
|---|---|---|
| committer | Joe Nash <Joseph.Nash@amd.com> | 2022-05-25 14:59:16 -0400 |
| commit | ef1ea5ac01332948c1fca260bba04110cf65f29b (patch) | |
| tree | c4418f8c51053bd1ce6a34250a129adfa70188fd /llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp | |
| parent | 1a51ab766f471059abe6ae9123512d2137e2e0af (diff) | |
| download | llvm-ef1ea5ac01332948c1fca260bba04110cf65f29b.zip llvm-ef1ea5ac01332948c1fca260bba04110cf65f29b.tar.gz llvm-ef1ea5ac01332948c1fca260bba04110cf65f29b.tar.bz2 | |
[AMDGPU] gfx11 vinterp instructions MC support
A new instruction encoding. Some of these instructions were previously VOP3
encoded.
Contributors:
Carl Ritson <carl.ritson@amd.com>
Patch 11/N for upstreaming of AMDGPU gfx11 architecture.
Depends on D125824
Reviewed By: critson
Differential Revision: https://reviews.llvm.org/D125989
Diffstat (limited to 'llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions