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| author | Luke Lau <luke@igalia.com> | 2024-05-10 10:01:23 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-05-10 10:01:23 +0800 |
| commit | d24eaef92525d03b4b64c7b4acd07197bdfb57cc (patch) | |
| tree | 8116a3a5cc64cdbe7629f0eca8c141c50f585009 /llvm/lib/Target/RISCV/RISCVISelLowering.cpp | |
| parent | db78ee0cb82669302a5e0f18a15fd53346a73823 (diff) | |
| download | llvm-d24eaef92525d03b4b64c7b4acd07197bdfb57cc.zip llvm-d24eaef92525d03b4b64c7b4acd07197bdfb57cc.tar.gz llvm-d24eaef92525d03b4b64c7b4acd07197bdfb57cc.tar.bz2 | |
[RISCV] Sink vector select splat operands (#91554)
vmerge.vxm allows us to splat the true operand of a select, so sink it
where possible to reduce vector register pressure.
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 00a97d15..e093798 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -2019,6 +2019,7 @@ bool RISCVTargetLowering::canSplatOperand(unsigned Opcode, int Operand) const { case Instruction::SDiv: case Instruction::URem: case Instruction::SRem: + case Instruction::Select: return Operand == 1; default: return false; |