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| author | Christian Konig <christian.koenig@amd.com> | 2013-02-16 11:28:22 +0000 |
|---|---|---|
| committer | Christian Konig <christian.koenig@amd.com> | 2013-02-16 11:28:22 +0000 |
| commit | c756cb9901e4455da9d1fcf0a619dd4fe008e205 (patch) | |
| tree | ae05903c5f1d4b3f03f67b40b76341f01ffef622 /llvm/lib/Target/R600/SILowerControlFlow.cpp | |
| parent | b9e281a723933b8ced8dddf52a1887828b7f6f57 (diff) | |
| download | llvm-c756cb9901e4455da9d1fcf0a619dd4fe008e205.zip llvm-c756cb9901e4455da9d1fcf0a619dd4fe008e205.tar.gz llvm-c756cb9901e4455da9d1fcf0a619dd4fe008e205.tar.bz2 | |
R600/SI: cleanup literal handling v3
Seems to be allot simpler, and also paves the
way for further improvements.
v2: rebased on master, use 0 in BUFFER_LOAD_FORMAT_XYZW,
use VGPR0 in dummy EXP, avoid compiler warning, break
after encoding the first literal.
v3: correctly use V_ADD_F32_e64
This is a candidate for the stable branch.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 175354
Diffstat (limited to 'llvm/lib/Target/R600/SILowerControlFlow.cpp')
| -rw-r--r-- | llvm/lib/Target/R600/SILowerControlFlow.cpp | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/lib/Target/R600/SILowerControlFlow.cpp b/llvm/lib/Target/R600/SILowerControlFlow.cpp index 1b0dbcc..b215aa2 100644 --- a/llvm/lib/Target/R600/SILowerControlFlow.cpp +++ b/llvm/lib/Target/R600/SILowerControlFlow.cpp @@ -158,10 +158,10 @@ void SILowerControlFlowPass::SkipIfDead(MachineInstr &MI) { .addImm(0) .addImm(1) .addImm(1) - .addReg(AMDGPU::SREG_LIT_0) - .addReg(AMDGPU::SREG_LIT_0) - .addReg(AMDGPU::SREG_LIT_0) - .addReg(AMDGPU::SREG_LIT_0); + .addReg(AMDGPU::VGPR0) + .addReg(AMDGPU::VGPR0) + .addReg(AMDGPU::VGPR0) + .addReg(AMDGPU::VGPR0); // ... and terminate wavefront BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM)); @@ -296,7 +296,7 @@ void SILowerControlFlowPass::Kill(MachineInstr &MI) { // Clear this pixel from the exec mask if the operand is negative BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMPX_LE_F32_e32), AMDGPU::VCC) - .addReg(AMDGPU::SREG_LIT_0) + .addImm(0) .addOperand(MI.getOperand(0)); MI.eraseFromParent(); |