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| author | Michel Danzer <michel.daenzer@amd.com> | 2014-02-27 01:47:02 +0000 |
|---|---|---|
| committer | Michel Danzer <michel.daenzer@amd.com> | 2014-02-27 01:47:02 +0000 |
| commit | 6f273c57db5862a11ed8646f54feb766c4dbe72c (patch) | |
| tree | 19e6e049ad07077a4a858b794066fddb6d4d6b4c /llvm/lib/Target/R600/SILowerControlFlow.cpp | |
| parent | 294c08265dbd9ba80e0e8fda22dbe93775b25b11 (diff) | |
| download | llvm-6f273c57db5862a11ed8646f54feb766c4dbe72c.zip llvm-6f273c57db5862a11ed8646f54feb766c4dbe72c.tar.gz llvm-6f273c57db5862a11ed8646f54feb766c4dbe72c.tar.bz2 | |
R600/SI: Allow SI_KILL for geometry shaders
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 202336
Diffstat (limited to 'llvm/lib/Target/R600/SILowerControlFlow.cpp')
| -rw-r--r-- | llvm/lib/Target/R600/SILowerControlFlow.cpp | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/llvm/lib/Target/R600/SILowerControlFlow.cpp b/llvm/lib/Target/R600/SILowerControlFlow.cpp index f6f9016..fa5ee16 100644 --- a/llvm/lib/Target/R600/SILowerControlFlow.cpp +++ b/llvm/lib/Target/R600/SILowerControlFlow.cpp @@ -145,7 +145,9 @@ void SILowerControlFlowPass::SkipIfDead(MachineInstr &MI) { MachineBasicBlock &MBB = *MI.getParent(); DebugLoc DL = MI.getDebugLoc(); - if (!shouldSkip(&MBB, &MBB.getParent()->back())) + if (MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType != + ShaderType::PIXEL || + !shouldSkip(&MBB, &MBB.getParent()->back())) return; MachineBasicBlock::iterator Insert = &MI; @@ -293,9 +295,11 @@ void SILowerControlFlowPass::Kill(MachineInstr &MI) { MachineBasicBlock &MBB = *MI.getParent(); DebugLoc DL = MI.getDebugLoc(); - // Kill is only allowed in pixel shaders + // Kill is only allowed in pixel / geometry shaders assert(MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType == - ShaderType::PIXEL); + ShaderType::PIXEL || + MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType == + ShaderType::GEOMETRY); // Clear this pixel from the exec mask if the operand is negative BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMPX_LE_F32_e32), AMDGPU::VCC) |