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| author | Michel Danzer <michel.daenzer@amd.com> | 2013-07-10 16:36:43 +0000 |
|---|---|---|
| committer | Michel Danzer <michel.daenzer@amd.com> | 2013-07-10 16:36:43 +0000 |
| commit | 1c45430e763e78736fcc2c8a474e0add971138f7 (patch) | |
| tree | 072fe304dc4eebbfae0f03fd90bfc626b12a938f /llvm/lib/Target/R600/SILowerControlFlow.cpp | |
| parent | 83f87c4c2efc018ec8ba7621bc7d60c05be9b69f (diff) | |
| download | llvm-1c45430e763e78736fcc2c8a474e0add971138f7.zip llvm-1c45430e763e78736fcc2c8a474e0add971138f7.tar.gz llvm-1c45430e763e78736fcc2c8a474e0add971138f7.tar.bz2 | |
R600/SI: Initial support for LDS/GDS instructions
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186009
Diffstat (limited to 'llvm/lib/Target/R600/SILowerControlFlow.cpp')
| -rw-r--r-- | llvm/lib/Target/R600/SILowerControlFlow.cpp | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/llvm/lib/Target/R600/SILowerControlFlow.cpp b/llvm/lib/Target/R600/SILowerControlFlow.cpp index 5b434fb..c2e8f02 100644 --- a/llvm/lib/Target/R600/SILowerControlFlow.cpp +++ b/llvm/lib/Target/R600/SILowerControlFlow.cpp @@ -411,6 +411,7 @@ bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) { TRI = MF.getTarget().getRegisterInfo(); bool HaveKill = false; + bool NeedM0 = false; bool NeedWQM = false; unsigned Depth = 0; @@ -482,6 +483,13 @@ bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) { IndirectDst(MI); break; + case AMDGPU::DS_READ_B32: + NeedWQM = true; + // Fall through + case AMDGPU::DS_WRITE_B32: + NeedM0 = true; + break; + case AMDGPU::V_INTERP_P1_F32: case AMDGPU::V_INTERP_P2_F32: case AMDGPU::V_INTERP_MOV_F32: @@ -492,6 +500,14 @@ bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) { } } + if (NeedM0) { + MachineBasicBlock &MBB = MF.front(); + // Initialize M0 to a value that won't cause LDS access to be discarded + // due to offset clamping + BuildMI(MBB, MBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_MOV_B32), + AMDGPU::M0).addImm(0xffffffff); + } + if (NeedWQM) { MachineBasicBlock &MBB = MF.front(); BuildMI(MBB, MBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_WQM_B64), |