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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-08-01 15:23:42 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-08-01 15:23:42 +0000 |
| commit | 0344cdfe390842fd62e73a8a0cb4eb495c355076 (patch) | |
| tree | cbee5af8711fa2a8d8b8c137fa19b415d699a24f /llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp | |
| parent | 53698938a47b6ee20542a0619908932acd07f7d5 (diff) | |
| download | llvm-0344cdfe390842fd62e73a8a0cb4eb495c355076.zip llvm-0344cdfe390842fd62e73a8a0cb4eb495c355076.tar.gz llvm-0344cdfe390842fd62e73a8a0cb4eb495c355076.tar.bz2 | |
R600: Add 64-bit float load/store support
* Added R600_Reg64 class
* Added T#Index#.XY registers definition
* Added v2i32 register reads from parameter and global space
* Added f32 and i32 elements extraction from v2f32 and v2i32
* Added v2i32 -> v2f32 conversions
Tom Stellard:
- Mark vec2 operations as expand. The addition of a vec2 register
class made them all legal.
Patch by: Dmitry Cherkassov
Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com>
llvm-svn: 187582
Diffstat (limited to 'llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp')
| -rw-r--r-- | llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp b/llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp index cc45891..715be37 100644 --- a/llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp +++ b/llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp @@ -378,8 +378,10 @@ public: case AMDGPU::R600_ExportBuf: case AMDGPU::R600_ExportSwz: case AMDGPU::RAT_WRITE_CACHELESS_32_eg: + case AMDGPU::RAT_WRITE_CACHELESS_64_eg: case AMDGPU::RAT_WRITE_CACHELESS_128_eg: - case AMDGPU::RAT_STORE_DWORD_cm: + case AMDGPU::RAT_STORE_DWORD32_cm: + case AMDGPU::RAT_STORE_DWORD64_cm: DEBUG(dbgs() << CfCount << ":"; MI->dump();); CfCount++; break; |