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| author | Chris Lattner <sabre@nondot.org> | 2006-06-16 17:34:12 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-06-16 17:34:12 +0000 |
| commit | a35f306740182bd02191f573983dbea0a0036ecd (patch) | |
| tree | dda049ba457302630fb70f8c45e33d3a44c95b61 /llvm/lib/Target/PowerPC/PPCSubtarget.cpp | |
| parent | 29052c849fac31468cea718890c90026fd177072 (diff) | |
| download | llvm-a35f306740182bd02191f573983dbea0a0036ecd.zip llvm-a35f306740182bd02191f573983dbea0a0036ecd.tar.gz llvm-a35f306740182bd02191f573983dbea0a0036ecd.tar.bz2 | |
Rename some subtarget features. A CPU now can *have* 64-bit instructions,
can in 32-bit mode we can choose to optionally *use* 64-bit registers.
llvm-svn: 28824
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCSubtarget.cpp')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCSubtarget.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp index 607771b..b228ba7 100644 --- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp +++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp @@ -73,8 +73,8 @@ PPCSubtarget::PPCSubtarget(const Module &M, const std::string &FS, bool is64Bit) : StackAlignment(16) , InstrItins() , IsGigaProcessor(false) - , Is64Bit(false) - , Has64BitRegs(false) + , Has64BitSupport(false) + , Use64BitRegs(false) , HasAltivec(false) , HasFSQRT(false) , HasSTFIWX(false) |