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authorKazu Hirata <kazu@google.com>2022-09-03 11:17:40 -0700
committerKazu Hirata <kazu@google.com>2022-09-03 11:17:40 -0700
commitfedc59734a44ef7b62c5f389b0cdffd02264b2a9 (patch)
tree78e86a59879b3ba34f94703fc76139a3b00690de /llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
parentff2fe7b82974e01c61f4f7247be231182fb76591 (diff)
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[llvm] Use range-based for loops (NFC)
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp')
-rw-r--r--llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp13
1 files changed, 6 insertions, 7 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 5ab1043..5d52007 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -404,9 +404,8 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
// Reserve Altivec registers when Altivec is unavailable.
if (!Subtarget.hasAltivec())
- for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(),
- IE = PPC::VRRCRegClass.end(); I != IE; ++I)
- markSuperRegs(Reserved, *I);
+ for (MCRegister Reg : PPC::VRRCRegClass)
+ markSuperRegs(Reserved, Reg);
if (Subtarget.isAIXABI() && Subtarget.hasAltivec() &&
!TM.getAIXExtendedAltivecABI()) {
@@ -465,13 +464,13 @@ bool PPCRegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF) co
// The callee saved info is valid so it can be traversed.
// Checking for registers that need saving that do not have load or store
// forms where the address offset is an immediate.
- for (unsigned i = 0; i < Info.size(); i++) {
+ for (const CalleeSavedInfo &CSI : Info) {
// If the spill is to a register no scavenging is required.
- if (Info[i].isSpilledToReg())
+ if (CSI.isSpilledToReg())
continue;
- int FrIdx = Info[i].getFrameIdx();
- Register Reg = Info[i].getReg();
+ int FrIdx = CSI.getFrameIdx();
+ Register Reg = CSI.getReg();
const TargetRegisterClass *RC = getMinimalPhysRegClass(Reg);
unsigned Opcode = InstrInfo->getStoreOpcodeForSpill(RC);