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author | Hal Finkel <hfinkel@anl.gov> | 2015-02-01 15:03:28 +0000 |
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committer | Hal Finkel <hfinkel@anl.gov> | 2015-02-01 15:03:28 +0000 |
commit | e6698d5305a29a186e035ab737931a139d70bcd2 (patch) | |
tree | b8a181eaaaf86cc20444f94cf9b7f23a96e5c02d /llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | |
parent | 1b3961c0195acc5bca165743a101b2f4e5717edb (diff) | |
download | llvm-e6698d5305a29a186e035ab737931a139d70bcd2.zip llvm-e6698d5305a29a186e035ab737931a139d70bcd2.tar.gz llvm-e6698d5305a29a186e035ab737931a139d70bcd2.tar.bz2 |
[PowerPC] Make r2 allocatable on PPC64/ELF for some leaf functions
The TOC base pointer is passed in r2, and we normally reserve this register so
that we can depend on it being there. However, for leaf functions, and
specifically those leaf functions that don't do any TOC access of their own
(which is generally due to accessing the constant pool, using TLS, etc.),
we can treat r2 as an ordinary callee-saved register (it must be callee-saved
because, for local direct calls, the linker will not insert any save/restore
code).
The allocation order has been changed slightly for PPC64/ELF systems to put r2
at the end of the list (while leaving it near the beginning for Darwin systems
to prevent unnecessary output changes). While r2 is allocatable, using it still
requires spill/restore traffic, and thus comes at the end of the list.
llvm-svn: 227745
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp')
-rw-r--r-- | llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp index 2645b1c..b0b20a0 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -115,9 +115,14 @@ PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { CSR_Darwin32_Altivec_SaveList : CSR_Darwin32_SaveList); + // On PPC64, we might need to save r2 (but only if it is not reserved). + bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2); + return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? - CSR_SVR464_Altivec_SaveList : - CSR_SVR464_SaveList) : + (SaveR2 ? CSR_SVR464_R2_Altivec_SaveList : + CSR_SVR464_Altivec_SaveList) : + (SaveR2 ? CSR_SVR464_R2_SaveList : + CSR_SVR464_SaveList)) : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_SaveList : CSR_SVR432_SaveList); @@ -216,7 +221,16 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. if (Subtarget.isSVR4ABI()) { - Reserved.set(PPC::X2); + // We only reserve r2 if we need to use the TOC pointer. If we have no + // explicit uses of the TOC pointer (meaning we're a leaf function with + // no constant-pool loads, etc.) and we have no potential uses inside an + // inline asm block, then we can treat r2 has an ordinary callee-saved + // register. + const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); + if (FuncInfo->usesTOCBasePtr() || MF.hasInlineAsm()) + Reserved.set(PPC::X2); + else + Reserved.reset(PPC::R2); } } |