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authorzhijian lin <zhijian@ca.ibm.com>2024-05-29 10:53:00 -0400
committerGitHub <noreply@github.com>2024-05-29 10:53:00 -0400
commit6127f15e5b4834411e8f2e700e25c40490deec35 (patch)
treec320895a4d2cc11c16fd04520c7c019b9e31099b /llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
parent975477e7f7ee1d8c29975224abb452f73b90db36 (diff)
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[PowerPC] option `-msoft-float` should not block the PC-relative address instruction (#92543)
The Prefix instruction is introduced on PowerPC ISA3_1. In the PR, 1. The `FeaturePrefixInstrs` do not imply the `FeatureP8Vector` ,`FeatureP9Vector` . 2. `FeaturePrefixInstrs` implies only the FeatureISA3_1. 3. For the prefix instructions `paddi` and `pli` , they have `Predicates = [PrefixInstrs] ` 4. For the prefix instructions `plfs` and `plfd`, they have `Predicates = [PrefixInstrs, HasFPU] ` 5. For the prefix instructions "plxv` , "plxssp` and `plxsd` , they have `Predicates = [PrefixInstrs, HasP10Vector]` Fixes #62372
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp')
-rw-r--r--llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 7e4cd6c..9e8da59 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -1695,7 +1695,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
// transform it to the prefixed version so we don't have to use the XForm.
if ((OpC == PPC::LXVP || OpC == PPC::STXVP) &&
(!isInt<16>(Offset) || (Offset % offsetMinAlign(MI)) != 0) &&
- Subtarget.hasPrefixInstrs()) {
+ Subtarget.hasPrefixInstrs() && Subtarget.hasP10Vector()) {
unsigned NewOpc = OpC == PPC::LXVP ? PPC::PLXVP : PPC::PSTXVP;
MI.setDesc(TII.get(NewOpc));
OpC = NewOpc;