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| author | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2016-05-09 18:54:58 +0000 |
|---|---|---|
| committer | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2016-05-09 18:54:58 +0000 |
| commit | 6e29baf7f529fe7e5fbd1bff1037a02ef7e25a28 (patch) | |
| tree | 99cd6680860575e5a08e1d5dc04646caf2b4fa9e /llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | |
| parent | da7fe0c4a4954145844c01d86886a7b77b70f861 (diff) | |
| download | llvm-6e29baf7f529fe7e5fbd1bff1037a02ef7e25a28.zip llvm-6e29baf7f529fe7e5fbd1bff1037a02ef7e25a28.tar.gz llvm-6e29baf7f529fe7e5fbd1bff1037a02ef7e25a28.tar.bz2 | |
[Power9] Add support for -mcpu=pwr9 in the back end
This patch corresponds to review:
http://reviews.llvm.org/D19683
Simply adds the bits for being able to specify -mcpu=pwr9 to the back end.
llvm-svn: 268950
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index 204dc28..313ab88 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -93,6 +93,7 @@ PPCInstrInfo::CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, unsigned Directive = DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective(); + // FIXME: Leaving this as-is until we have POWER9 scheduling info if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8) return new PPCDispatchGroupSBHazardRecognizer(II, DAG); @@ -181,6 +182,7 @@ int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, case PPC::DIR_PWR6X: case PPC::DIR_PWR7: case PPC::DIR_PWR8: + // FIXME: Is this needed for POWER9? Latency += 2; break; } @@ -428,6 +430,8 @@ void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB, case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break; case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break; case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */ + // FIXME: Update when POWER9 scheduling model is ready. + case PPC::DIR_PWR9: Opcode = PPC::NOP_GT_PWR7; break; } DebugLoc DL; |