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author | Chuang-Yu Cheng <cycheng@multicorewareinc.com> | 2016-04-12 03:04:44 +0000 |
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committer | Chuang-Yu Cheng <cycheng@multicorewareinc.com> | 2016-04-12 03:04:44 +0000 |
commit | 6efde2fb451bf6c5538ca38cfb44cf84a7bb0e72 (patch) | |
tree | a1c02d803a815144b37a07df7672365b45ada2ce /llvm/lib/Target/PowerPC/PPCFrameLowering.cpp | |
parent | 9b3f99e50f5aff081352f362c1923e2dd3ed3aaf (diff) | |
download | llvm-6efde2fb451bf6c5538ca38cfb44cf84a7bb0e72.zip llvm-6efde2fb451bf6c5538ca38cfb44cf84a7bb0e72.tar.gz llvm-6efde2fb451bf6c5538ca38cfb44cf84a7bb0e72.tar.bz2 |
[PPC64] Use mfocrf in prologue when we only need to save 1 nonvolatile CR field
In the ELFv2 ABI, we are not required to save all CR fields. If only one
nonvolatile CR field is clobbered, use mfocrf instead of mfcr to
selectively save the field, because mfocrf has short latency compares to
mfcr.
Thanks Nemanja's invaluable hint!
Reviewers: nemanjai tjablin hfinkel kbarton
http://reviews.llvm.org/D17749
llvm-svn: 266038
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCFrameLowering.cpp')
-rw-r--r-- | llvm/lib/Target/PowerPC/PPCFrameLowering.cpp | 24 |
1 files changed, 16 insertions, 8 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp index aadf64d..40a2e8b 100644 --- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp @@ -838,11 +838,15 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF, // If we need to spill the CR and the LR but we don't have two separate // registers available, we must spill them one at a time if (MustSaveCR && SingleScratchReg && MustSaveLR) { - // FIXME: In the ELFv2 ABI, we are not required to save all CR fields. - // If only one or two CR fields are clobbered, it could be more - // efficient to use mfocrf to selectively save just those fields. + // In the ELFv2 ABI, we are not required to save all CR fields. + // If only one or two CR fields are clobbered, it is more efficient to use + // mfocrf to selectively save just those fields, because mfocrf has short + // latency compares to mfcr. + unsigned MfcrOpcode = PPC::MFCR8; + if (isELFv2ABI && MustSaveCRs.size() == 1) + MfcrOpcode = PPC::MFOCRF8; MachineInstrBuilder MIB = - BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg); + BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg); for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill); BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8)) @@ -856,11 +860,15 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF, if (MustSaveCR && !(SingleScratchReg && MustSaveLR)) { // will only occur for PPC64 - // FIXME: In the ELFv2 ABI, we are not required to save all CR fields. - // If only one or two CR fields are clobbered, it could be more - // efficient to use mfocrf to selectively save just those fields. + // In the ELFv2 ABI, we are not required to save all CR fields. + // If only one or two CR fields are clobbered, it is more efficient to use + // mfocrf to selectively save just those fields, because mfocrf has short + // latency compares to mfcr. + unsigned MfcrOpcode = PPC::MFCR8; + if (isELFv2ABI && MustSaveCRs.size() == 1) + MfcrOpcode = PPC::MFOCRF8; MachineInstrBuilder MIB = - BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg); + BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg); for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill); } |