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| author | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2016-02-29 16:42:27 +0000 |
|---|---|---|
| committer | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2016-02-29 16:42:27 +0000 |
| commit | 1a5706ca1bbf4028fb01424238ae1d22f0f64ba6 (patch) | |
| tree | b7564d1e5b9e850fe07f000554f7b1dbb17eae6e /llvm/lib/Target/PowerPC/PPCFastISel.cpp | |
| parent | 4823631af475410cb7c2c47af28ed010bf956d45 (diff) | |
| download | llvm-1a5706ca1bbf4028fb01424238ae1d22f0f64ba6.zip llvm-1a5706ca1bbf4028fb01424238ae1d22f0f64ba6.tar.gz llvm-1a5706ca1bbf4028fb01424238ae1d22f0f64ba6.tar.bz2 | |
Fix for PR26180
Corresponds to Phabricator review:
http://reviews.llvm.org/D16592
This fix includes both an update to how we handle the "generic" CPU on LE
systems as well as Anton's fix for the Fast Isel issue.
llvm-svn: 262233
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCFastISel.cpp')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCFastISel.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCFastISel.cpp b/llvm/lib/Target/PowerPC/PPCFastISel.cpp index 3980ecf..1de2679 100644 --- a/llvm/lib/Target/PowerPC/PPCFastISel.cpp +++ b/llvm/lib/Target/PowerPC/PPCFastISel.cpp @@ -1068,10 +1068,10 @@ unsigned PPCFastISel::PPCMoveToIntReg(const Instruction *I, MVT VT, if (!PPCEmitStore(MVT::f64, SrcReg, Addr)) return 0; - // Reload it into a GPR. If we want an i32, modify the address - // to have a 4-byte offset so we load from the right place. + // Reload it into a GPR. If we want an i32 on big endian, modify the + // address to have a 4-byte offset so we load from the right place. if (VT == MVT::i32) - Addr.Offset = 4; + Addr.Offset = (PPCSubTarget->isLittleEndian()) ? 0 : 4; // Look at the currently assigned register for this instruction // to determine the required register class. |