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author | Hal Finkel <hfinkel@anl.gov> | 2014-05-11 16:23:29 +0000 |
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committer | Hal Finkel <hfinkel@anl.gov> | 2014-05-11 16:23:29 +0000 |
commit | c4c6c8766657cdec2fd30b23a5b3890f12f1f2be (patch) | |
tree | 859a3937c212878db256878c78ec7040e4553cdd /llvm/lib/Target/PowerPC/PPCCTRLoops.cpp | |
parent | 60cae1ba49a4074ec130448a08f55b7078b64ef9 (diff) | |
download | llvm-c4c6c8766657cdec2fd30b23a5b3890f12f1f2be.zip llvm-c4c6c8766657cdec2fd30b23a5b3890f12f1f2be.tar.gz llvm-c4c6c8766657cdec2fd30b23a5b3890f12f1f2be.tar.bz2 |
[PowerPC] On PPC32, 128-bit shifts might be runtime calls
The counter-loops formation pass needs to know what operations might be
function calls (because they can't appear in counter-based loops). On PPC32,
128-bit shifts might be runtime calls (even though you can't use __int128 on
PPC32, it seems that SROA might form them).
Fixes PR19709.
llvm-svn: 208501
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCCTRLoops.cpp')
-rw-r--r-- | llvm/lib/Target/PowerPC/PPCCTRLoops.cpp | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp b/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp index 7749c08..ec1e34d 100644 --- a/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp +++ b/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp @@ -370,6 +370,14 @@ bool PPCCTRLoops::mightUseCTR(const Triple &TT, BasicBlock *BB) { J->getOpcode() == Instruction::URem || J->getOpcode() == Instruction::SRem)) { return true; + } else if (TT.isArch32Bit() && + isLargeIntegerTy(false, J->getType()->getScalarType()) && + (J->getOpcode() == Instruction::Shl || + J->getOpcode() == Instruction::AShr || + J->getOpcode() == Instruction::LShr)) { + // Only on PPC32, for 128-bit integers (specifically not 64-bit + // integers), these might be runtime calls. + return true; } else if (isa<IndirectBrInst>(J) || isa<InvokeInst>(J)) { // On PowerPC, indirect jumps use the counter register. return true; |