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| author | Sanjay Patel <spatel@rotateright.com> | 2018-09-09 14:13:22 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2018-09-09 14:13:22 +0000 |
| commit | 6ebf218e4c6e168f7e34101018121a67c2625123 (patch) | |
| tree | 4e03b1d49b3864b256a32557f74ae9001a7b10b9 /llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp | |
| parent | fd1dc75b40ceeae4d63e7ad13e78fff2d5ba9f1b (diff) | |
| download | llvm-6ebf218e4c6e168f7e34101018121a67c2625123.zip llvm-6ebf218e4c6e168f7e34101018121a67c2625123.tar.gz llvm-6ebf218e4c6e168f7e34101018121a67c2625123.tar.bz2 | |
[SelectionDAG] enhance vector demanded elements to look at a vector select condition operand
This is the DAG equivalent of D51433.
If we know we're not using all vector lanes, use that knowledge to potentially simplify a vselect condition.
The reduction/horizontal tests show that we are eliminating AVX1 operations on the upper half of 256-bit
vectors because we don't need those anyway.
I'm not sure what the pr34592 test is showing. That's run with -O0; is SimplifyDemandedVectorElts supposed
to be running there?
Differential Revision: https://reviews.llvm.org/D51696
llvm-svn: 341762
Diffstat (limited to 'llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions
