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| author | James Y Knight <jyknight@google.com> | 2022-11-08 17:11:05 -0500 |
|---|---|---|
| committer | James Y Knight <jyknight@google.com> | 2023-02-02 15:28:45 -0500 |
| commit | 4b43ef3e5c37459996ce0f53615881f436cb0e65 (patch) | |
| tree | 5bda7d1374ae6bed8f9e3f33c6b9d3d85324ff13 /llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp | |
| parent | 9fe7d38e240a04cfb19cbc205542c4006bd2ba26 (diff) | |
| download | llvm-4b43ef3e5c37459996ce0f53615881f436cb0e65.zip llvm-4b43ef3e5c37459996ce0f53615881f436cb0e65.tar.gz llvm-4b43ef3e5c37459996ce0f53615881f436cb0e65.tar.bz2 | |
[PowerPC] Switch to by-name matching for instructions (part 1 of 2).
This is a follow-on to https://reviews.llvm.org/D134073.
After https://reviews.llvm.org/D137653 we can now switch the PPC
target away from positional operand matching.
This patch fixes all of the "easy" cases. While this changes a large
number of lines of tablegen source, it results in only a single
non-comment change in the code generated by tablegen: the (unused)
codegen-only "MTVRSAVEv" instruction was previously incorrectly
encoding operand 0, and now encodes (correctly) operand 1.
Changes which result in generated-code changes have been split off
into the next (smaller) patch, for ease of review.
Reviewed By: barannikov88
Differential Revision: https://reviews.llvm.org/D137661
Diffstat (limited to 'llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions