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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-01-26 09:30:08 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-01-26 09:30:08 +0000 |
| commit | 46696ef93c64d60864858d9bd1e76e62d64965ee (patch) | |
| tree | 4fc365d431a01a60e688e38130c23ab2690658f7 /llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp | |
| parent | c9655d9bd5c6053af394c23701977a42d50209cc (diff) | |
| download | llvm-46696ef93c64d60864858d9bd1e76e62d64965ee.zip llvm-46696ef93c64d60864858d9bd1e76e62d64965ee.tar.gz llvm-46696ef93c64d60864858d9bd1e76e62d64965ee.tar.bz2 | |
[X86][SSE] Add zero element and general 64-bit VZEXT_LOAD support to EltsFromConsecutiveLoads
This patch adds support for trailing zero elements to VZEXT_LOAD loads (and checks that no zero elts occur within the consecutive load).
It also generalizes the 64-bit VZEXT_LOAD load matching to work for loads other than 2x32-bit loads.
After this patch it will also be easier to add support for other basic load patterns like 32-bit VZEXT_LOAD loads, PMOVZX and subvector load insertion.
Differential Revision: http://reviews.llvm.org/D16217
llvm-svn: 258798
Diffstat (limited to 'llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions