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| author | Tim Northover <t.p.northover@gmail.com> | 2020-07-27 14:37:14 +0100 |
|---|---|---|
| committer | Tim Northover <t.p.northover@gmail.com> | 2020-07-28 13:31:17 +0100 |
| commit | 39108f4c7a2c52be88f73bd6abaa613f4b28d327 (patch) | |
| tree | 7b6a1305ea0e22f1cec2de6932c5e309851e3ee7 /llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp | |
| parent | 6d10d317d8b0f1975dbb17850efd7c069f6ee8fd (diff) | |
| download | llvm-39108f4c7a2c52be88f73bd6abaa613f4b28d327.zip llvm-39108f4c7a2c52be88f73bd6abaa613f4b28d327.tar.gz llvm-39108f4c7a2c52be88f73bd6abaa613f4b28d327.tar.bz2 | |
ARM: make Thumb1 instructions non-flag-setting in IT block.
Many Thumb1 instructions are defined to set CPSR if executed outside an IT
block, but leave it alone from inside one. In MachineIR this is represented by
whether an optional register is CPSR or NoReg (0), and affects how the
instructions are printed.
This sets the instruction to the appropriate form during if-conversion.
Diffstat (limited to 'llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions