diff options
| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2021-04-09 15:51:53 +0100 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2021-04-09 15:52:03 +0100 |
| commit | 245036950a7a63f77aa1f06f46dfe2fbb2cafc0f (patch) | |
| tree | 38a73c4b6f112983df1d5e42602dd9d5864857c0 /llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp | |
| parent | f3d7536b24f1d65c09de4899a51d9fdda83c3b1d (diff) | |
| download | llvm-245036950a7a63f77aa1f06f46dfe2fbb2cafc0f.zip llvm-245036950a7a63f77aa1f06f46dfe2fbb2cafc0f.tar.gz llvm-245036950a7a63f77aa1f06f46dfe2fbb2cafc0f.tar.bz2 | |
[X86][BMI] Fold cmpeq/ne(or(X,Y),X) --> cmpeq/ne(and(~X,Y),0) (PR44136)
I've initially just enabled this for BMI which has the ANDN instruction for i32/i64 - the i16/i8 cases give an idea of what'd we get when we enable it in all cases (I'll do this as a later commit).
Additionally, the i16/i8 cases could be freely promoted to i32 (as the args are already zeroext) and we could then make use of ANDN + the free cmp0 there as well - this has come up in PR48768 and PR49028 so I'm going to look at this soon.
https://alive2.llvm.org/ce/z/QVWHP_
https://alive2.llvm.org/ce/z/pLngT-
Vector cases do not appear to benefit from this as we end up with having to generate the zero vector as well - this is one of the reasons I didn't try to tie this into hasAndNot/hasAndNotCompare.
Differential Revision: https://reviews.llvm.org/D100177
Diffstat (limited to 'llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions