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| author | Bradley Smith <bradley.smith@arm.com> | 2021-04-12 13:06:25 +0100 |
|---|---|---|
| committer | Bradley Smith <bradley.smith@arm.com> | 2021-04-15 13:52:47 +0100 |
| commit | 22c017f0f902598505b57a9a7147278a7b4dad87 (patch) | |
| tree | 03e3061016ef96c9f4d2d4c805032dbfd79400fc /llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp | |
| parent | ecf93a716c9ecf2e38898547df90323e239a623c (diff) | |
| download | llvm-22c017f0f902598505b57a9a7147278a7b4dad87.zip llvm-22c017f0f902598505b57a9a7147278a7b4dad87.tar.gz llvm-22c017f0f902598505b57a9a7147278a7b4dad87.tar.bz2 | |
[AArch64][NEON] Match (or (and -a b) (and (a+1) b)) => bit select
With this patch vbslq_f32(vnegq_s32(a), b, c) lowers to a BIT instruction.
Co-authored-by: Paul Walker <paul.walker@arm.com>
Differential Revision: https://reviews.llvm.org/D100304
Diffstat (limited to 'llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions