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| author | Kit Barton <kbarton@ca.ibm.com> | 2016-04-28 20:00:42 +0000 |
|---|---|---|
| committer | Kit Barton <kbarton@ca.ibm.com> | 2016-04-28 20:00:42 +0000 |
| commit | 7a1a9e01ad54cf12e53f0fa228784bf2c04f0811 (patch) | |
| tree | f6f0061db054c5267b5a4b8feca415e1753b7aff /llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp | |
| parent | 9c52767f362457d0cbd76292988a9a103d7f35bf (diff) | |
| download | llvm-7a1a9e01ad54cf12e53f0fa228784bf2c04f0811.zip llvm-7a1a9e01ad54cf12e53f0fa228784bf2c04f0811.tar.gz llvm-7a1a9e01ad54cf12e53f0fa228784bf2c04f0811.tar.bz2 | |
This reverts commit r265505.
Revert "[Power9] Implement add-pc, multiply-add, modulo, extend-sign-shift, random number, set bool, and dfp test significance".
This patch has caused a functional regression in SPEC2k6 namd, and a performance regression in mesa-pipe.
llvm-svn: 267927
Diffstat (limited to 'llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp')
| -rw-r--r-- | llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp | 22 |
1 files changed, 0 insertions, 22 deletions
diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp index 5545f36..4b526fc 100644 --- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp +++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp @@ -528,10 +528,6 @@ public: (Kind == Immediate && isInt<16>(getImm()) && (getImm() & 3) == 0); } bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); } - bool isD8RCRegNumber() const { return Kind == Immediate && - isUInt<5>(getImm()) && - // required even register id - !(getImm() & 0x1); } bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); } bool isCCRegNumber() const { return (Kind == Expression && isUInt<3>(getExprCRVal())) || @@ -594,11 +590,6 @@ public: Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); } - void addRegD8RCOperands(MCInst &Inst, unsigned N) const { - assert(N == 1 && "Invalid number of operands!"); - Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); - } - void addRegVRRCOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); @@ -1229,19 +1220,6 @@ void PPCAsmParser::ProcessInstruction(MCInst &Inst, Inst = TmpInst; break; } - // ISA3.0 Instructions: - case PPC::SUBPCIS: - case PPC::LNIA: { - MCInst TmpInst; - TmpInst.setOpcode(PPC::ADDPCIS); - TmpInst.addOperand(Inst.getOperand(0)); - if (Opcode == PPC::SUBPCIS) - addNegOperand(TmpInst, Inst.getOperand(1), getContext()); - else - TmpInst.addOperand(MCOperand::createImm(0)); - Inst = TmpInst; - break; - } } } |