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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2015-09-15 13:46:21 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2015-09-15 13:46:21 +0000 |
| commit | c40de480418dae6cd11df64528c0074229e83769 (patch) | |
| tree | b6ad2b016790cd1963f00068aa8a75f2a0990cea /llvm/lib/Target/Mips/MipsSubtarget.cpp | |
| parent | d1062bbd893a43004a19a65c414b0453cf3ca04d (diff) | |
| download | llvm-c40de480418dae6cd11df64528c0074229e83769.zip llvm-c40de480418dae6cd11df64528c0074229e83769.tar.gz llvm-c40de480418dae6cd11df64528c0074229e83769.tar.bz2 | |
Revert r247684 - Replace Triple with a new TargetTuple ...
LLDB needs to be updated in the same commit.
llvm-svn: 247686
Diffstat (limited to 'llvm/lib/Target/Mips/MipsSubtarget.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsSubtarget.cpp | 23 |
1 files changed, 11 insertions, 12 deletions
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp index 4d2dc07..bb23a39 100644 --- a/llvm/lib/Target/Mips/MipsSubtarget.cpp +++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp @@ -62,16 +62,16 @@ void MipsSubtarget::anchor() { } MipsSubtarget::MipsSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, bool little, const MipsTargetMachine &TM) - : MipsGenSubtargetInfo(TargetTuple(TT), CPU, FS), - MipsArchVersion(MipsDefault), IsLittle(little), IsSoftFloat(false), - IsSingleFloat(false), IsFPXX(false), NoABICalls(false), IsFP64bit(false), - UseOddSPReg(true), IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), - HasCnMips(false), HasMips3_32(false), HasMips3_32r2(false), - HasMips4_32(false), HasMips4_32r2(false), HasMips5_32r2(false), - InMips16Mode(false), InMips16HardFloat(Mips16HardFloat), - InMicroMipsMode(false), HasDSP(false), HasDSPR2(false), - AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false), - UseTCCInDIV(false), HasEVA(false), TM(TM), TargetTriple(TT), TSInfo(), + : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault), + IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false), + NoABICalls(false), IsFP64bit(false), UseOddSPReg(true), + IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false), + HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false), + HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false), + InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false), + HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), + HasMSA(false), UseTCCInDIV(false), HasEVA(false), TM(TM), + TargetTriple(TT), TSInfo(), InstrInfo( MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))), FrameLowering(MipsFrameLowering::create(*this)), @@ -142,8 +142,7 @@ CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const { MipsSubtarget & MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS, const TargetMachine &TM) { - std::string CPUName = - MIPS_MC::selectMipsCPU(TargetTuple(TM.getTargetTriple()), CPU); + std::string CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU); // Parse features string. ParseSubtargetFeatures(CPUName, FS); |