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author | Eric Christopher <echristo@gmail.com> | 2015-02-18 00:55:06 +0000 |
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committer | Eric Christopher <echristo@gmail.com> | 2015-02-18 00:55:06 +0000 |
commit | bbe6ff50f365da1dfb2164384fecde5e00282a7b (patch) | |
tree | 33213a22975a07b429b79bf98db6b643266d2a5f /llvm/lib/Target/Mips/MipsSubtarget.cpp | |
parent | 102061a4947c9a07db3b874ffe26724d6fd43683 (diff) | |
download | llvm-bbe6ff50f365da1dfb2164384fecde5e00282a7b.zip llvm-bbe6ff50f365da1dfb2164384fecde5e00282a7b.tar.gz llvm-bbe6ff50f365da1dfb2164384fecde5e00282a7b.tar.bz2 |
Unify selectMipsCPU implementations.
llvm-svn: 229595
Diffstat (limited to 'llvm/lib/Target/Mips/MipsSubtarget.cpp')
-rw-r--r-- | llvm/lib/Target/Mips/MipsSubtarget.cpp | 16 |
1 files changed, 2 insertions, 14 deletions
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp index db96799..566c1a9 100644 --- a/llvm/lib/Target/Mips/MipsSubtarget.cpp +++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp @@ -143,23 +143,11 @@ CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const { return CodeGenOpt::Aggressive; } -/// Select the Mips CPU for the given triple and cpu name. -/// FIXME: Merge with the copy in MipsMCTargetDesc.cpp -static StringRef selectMipsCPU(Triple TT, StringRef CPU) { - if (CPU.empty() || CPU == "generic") { - if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel) - CPU = "mips32"; - else - CPU = "mips64"; - } - return CPU; -} - MipsSubtarget & MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS, const TargetMachine &TM) { - std::string CPUName = selectMipsCPU(TargetTriple, CPU); - + std::string CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU); + // Parse features string. ParseSubtargetFeatures(CPUName, FS); // Initialize scheduling itinerary for the specified CPU. |