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authorRafael Espindola <rafael.espindola@gmail.com>2016-06-28 14:33:28 +0000
committerRafael Espindola <rafael.espindola@gmail.com>2016-06-28 14:33:28 +0000
commitb30e66b82c8f68825153035af076dc09a24e6ab4 (patch)
tree1e22fa9a9faae7d1cb9c11fa4f5734e35aa61c0a /llvm/lib/Target/Mips/MipsSubtarget.cpp
parent6f7c280a3ddefab85f0ff436c94e7f33a075abec (diff)
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Convert more cases to isPositionIndependent(). NFC.
llvm-svn: 274021
Diffstat (limited to 'llvm/lib/Target/Mips/MipsSubtarget.cpp')
-rw-r--r--llvm/lib/Target/Mips/MipsSubtarget.cpp6
1 files changed, 5 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp
index 20915379..3e7570f 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.cpp
+++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp
@@ -114,7 +114,7 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, const std::string &CPU,
report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
}
- if (NoABICalls && TM.getRelocationModel() == Reloc::PIC_)
+ if (NoABICalls && TM.isPositionIndependent())
report_fatal_error("position-independent code requires '-mabicalls'");
// Set UseSmallSection.
@@ -126,6 +126,10 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, const std::string &CPU,
}
}
+bool MipsSubtarget::isPositionIndependent() const {
+ return TM.isPositionIndependent();
+}
+
/// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
bool MipsSubtarget::enablePostRAScheduler() const { return true; }