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authorEric Christopher <echristo@gmail.com>2014-07-02 21:29:23 +0000
committerEric Christopher <echristo@gmail.com>2014-07-02 21:29:23 +0000
commit5f9fd210b34141f5eddea0aadbe792bff89c0ed7 (patch)
treeab6cf5b0d4c1dfeb292f006863901c20b38ce4d4 /llvm/lib/Target/Mips/MipsSubtarget.cpp
parent11dd5cf9f19d58b2e13e84959ea9ef086a040f35 (diff)
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Move the data layout and selection dag info from the mips target machine
down to the subtarget. llvm-svn: 212224
Diffstat (limited to 'llvm/lib/Target/Mips/MipsSubtarget.cpp')
-rw-r--r--llvm/lib/Target/Mips/MipsSubtarget.cpp36
1 files changed, 33 insertions, 3 deletions
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp
index 286d398..ac0ffc7 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.cpp
+++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp
@@ -72,6 +72,36 @@ static StringRef selectMipsCPU(Triple TT, StringRef CPU) {
void MipsSubtarget::anchor() { }
+static std::string computeDataLayout(const MipsSubtarget &ST) {
+ std::string Ret = "";
+
+ // There are both little and big endian mips.
+ if (ST.isLittle())
+ Ret += "e";
+ else
+ Ret += "E";
+
+ Ret += "-m:m";
+
+ // Pointers are 32 bit on some ABIs.
+ if (!ST.isABI_N64())
+ Ret += "-p:32:32";
+
+ // 8 and 16 bit integers only need no have natural alignment, but try to
+ // align them to 32 bits. 64 bit integers have natural alignment.
+ Ret += "-i8:8:32-i16:16:32-i64:64";
+
+ // 32 bit registers are always available and the stack is at least 64 bit
+ // aligned. On N64 64 bit registers are also available and the stack is
+ // 128 bit aligned.
+ if (ST.isABI_N64() || ST.isABI_N32())
+ Ret += "-n32:64-S128";
+ else
+ Ret += "-n32-S64";
+
+ return Ret;
+}
+
MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, bool little,
Reloc::Model _RM, MipsTargetMachine *_TM)
@@ -83,10 +113,10 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false),
- RM(_RM), OverrideMode(NoOverride), TM(_TM), TargetTriple(TT), JITInfo() {
+ RM(_RM), OverrideMode(NoOverride), TM(_TM), TargetTriple(TT),
+ DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS))),
+ TSInfo(DL), JITInfo() {
- initializeSubtargetDependencies(CPU, FS);
-
if (InMips16Mode && !TM->Options.UseSoftFloat) {
// Hard float for mips16 means essentially to compile as soft float
// but to use a runtime library for soft float that is written with