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| author | Matthias Braun <matze@braunis.de> | 2015-06-13 03:42:16 +0000 |
|---|---|---|
| committer | Matthias Braun <matze@braunis.de> | 2015-06-13 03:42:16 +0000 |
| commit | 39a2afc9417667902511b9c082d639e95d76e38f (patch) | |
| tree | 24dad3ac079be2814c5ac481474981029ead2ac7 /llvm/lib/Target/Mips/MipsSubtarget.cpp | |
| parent | 88e213159a3d0650db1a1ca4cd840e4bd87b12d2 (diff) | |
| download | llvm-39a2afc9417667902511b9c082d639e95d76e38f.zip llvm-39a2afc9417667902511b9c082d639e95d76e38f.tar.gz llvm-39a2afc9417667902511b9c082d639e95d76e38f.tar.bz2 | |
Rename TargetSubtargetInfo::enablePostMachineScheduler() to enablePostRAScheduler()
r213101 changed the behaviour of this method to not only affect the
PostMachineScheduler scheduler but also the PostRAScheduler scheduler,
renaming should make this fact clear. Also document that the preferred
way is to specify this in the scheduling model instead of overriding
this method.
Differential Revision: http://reviews.llvm.org/D10427
llvm-svn: 239659
Diffstat (limited to 'llvm/lib/Target/Mips/MipsSubtarget.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsSubtarget.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp index 450900e..f133246 100644 --- a/llvm/lib/Target/Mips/MipsSubtarget.cpp +++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp @@ -126,7 +126,7 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, const std::string &CPU, } /// This overrides the PostRAScheduler bit in the SchedModel for any CPU. -bool MipsSubtarget::enablePostMachineScheduler() const { return true; } +bool MipsSubtarget::enablePostRAScheduler() const { return true; } void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { CriticalPathRCs.clear(); |