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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-06-24 16:16:12 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-06-24 16:16:12 +0000 |
commit | faeaedf8e938696497021adcd5925e5741c72f62 (patch) | |
tree | 66d3c65d42cfac2b080183c6c79562d0c205b23f /llvm/lib/Target/Mips/MipsMachineFunction.cpp | |
parent | 906d494b6e7eb0d8bde19bec2de7d93a9516ebe3 (diff) | |
download | llvm-faeaedf8e938696497021adcd5925e5741c72f62.zip llvm-faeaedf8e938696497021adcd5925e5741c72f62.tar.gz llvm-faeaedf8e938696497021adcd5925e5741c72f62.tar.bz2 |
GlobalISel: Remove unsigned variant of SrcOp
Force using Register.
One downside is the generated register enums require explicit
conversion.
llvm-svn: 364194
Diffstat (limited to 'llvm/lib/Target/Mips/MipsMachineFunction.cpp')
-rw-r--r-- | llvm/lib/Target/Mips/MipsMachineFunction.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/Mips/MipsMachineFunction.cpp b/llvm/lib/Target/Mips/MipsMachineFunction.cpp index d489fac..85b20fc 100644 --- a/llvm/lib/Target/Mips/MipsMachineFunction.cpp +++ b/llvm/lib/Target/Mips/MipsMachineFunction.cpp @@ -44,14 +44,14 @@ static const TargetRegisterClass &getGlobalBaseRegClass(MachineFunction &MF) { return Mips::GPR32RegClass; } -unsigned MipsFunctionInfo::getGlobalBaseReg() { +Register MipsFunctionInfo::getGlobalBaseReg() { if (!GlobalBaseReg) GlobalBaseReg = MF.getRegInfo().createVirtualRegister(&getGlobalBaseRegClass(MF)); return GlobalBaseReg; } -unsigned MipsFunctionInfo::getGlobalBaseRegForGlobalISel() { +Register MipsFunctionInfo::getGlobalBaseRegForGlobalISel() { if (!GlobalBaseReg) { getGlobalBaseReg(); initGlobalBaseReg(); |