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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-11-18 11:53:36 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-11-18 11:53:36 +0000 |
| commit | dcd8433597238c67b1298f3703a9f53fd482d68f (patch) | |
| tree | eb572212c480df444de81b80504bbc81631c3036 /llvm/lib/Target/Mips/MipsMachineFunction.cpp | |
| parent | 5f7878964a5d264d1f460b653d7692e61727174a (diff) | |
| download | llvm-dcd8433597238c67b1298f3703a9f53fd482d68f.zip llvm-dcd8433597238c67b1298f3703a9f53fd482d68f.tar.gz llvm-dcd8433597238c67b1298f3703a9f53fd482d68f.tar.bz2 | |
Fix spelling mistakes in MIPS target comments. NFC.
Identified by Pedro Giffuni in PR27636.
llvm-svn: 287338
Diffstat (limited to 'llvm/lib/Target/Mips/MipsMachineFunction.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsMachineFunction.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/MipsMachineFunction.cpp b/llvm/lib/Target/Mips/MipsMachineFunction.cpp index e92d3ae..d0609b1 100644 --- a/llvm/lib/Target/Mips/MipsMachineFunction.cpp +++ b/llvm/lib/Target/Mips/MipsMachineFunction.cpp @@ -68,7 +68,7 @@ void MipsFunctionInfo::createEhDataRegsFI() { void MipsFunctionInfo::createISRRegFI() { // ISRs require spill slots for Status & ErrorPC Coprocessor 0 registers. // The current implementation only supports Mips32r2+ not Mips64rX. Status - // is always 32 bits, ErrorPC is 32 or 64 bits dependant on architecture, + // is always 32 bits, ErrorPC is 32 or 64 bits dependent on architecture, // however Mips32r2+ is the supported architecture. const TargetRegisterClass *RC = &Mips::GPR32RegClass; |