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| author | Craig Topper <craig.topper@intel.com> | 2019-05-31 07:38:26 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-05-31 07:38:26 +0000 |
| commit | 31d00d80a21ffbc5bc03c7b90de030b29660a3bd (patch) | |
| tree | a2b857102222464ecde9938d10c2998f82effd5d /llvm/lib/Target/Mips/MipsMachineFunction.cpp | |
| parent | cded5737109524d7cc756ac364a29cde835942b3 (diff) | |
| download | llvm-31d00d80a21ffbc5bc03c7b90de030b29660a3bd.zip llvm-31d00d80a21ffbc5bc03c7b90de030b29660a3bd.tar.gz llvm-31d00d80a21ffbc5bc03c7b90de030b29660a3bd.tar.bz2 | |
[X86] Remove patterns for X86VSintToFP/X86VUintToFP+loadv4f32 to v2f64.
These patterns can incorrectly narrow a volatile load from 128-bits to 64-bits.
Similar to PR42079.
Switch to using (v4i32 (bitcast (v2i64 (scalar_to_vector (loadi64))))) as the
load pattern used in the instructions.
This probably still has issues in 32-bit mode where loadi64 isn't legal. Maybe
we should use VZMOVL for widened loads even when we don't need the upper bits
as zeroes?
llvm-svn: 362203
Diffstat (limited to 'llvm/lib/Target/Mips/MipsMachineFunction.cpp')
0 files changed, 0 insertions, 0 deletions