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authorZlatko Buljan <Zlatko.Buljan@imgtec.com>2016-05-09 08:07:28 +0000
committerZlatko Buljan <Zlatko.Buljan@imgtec.com>2016-05-09 08:07:28 +0000
commitba553a6e0aad74d92be87ea5720719bcb2e2581f (patch)
treeff1a43684db7d8a276d30f2c81521c678d02a521 /llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
parent63a2083be9ffcb45a8894a4b874a821855ce8f46 (diff)
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[mips][microMIPS] Implement LWP and SWP instructions
Differential Revision: http://reviews.llvm.org/D10640 llvm-svn: 268896
Diffstat (limited to 'llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp')
-rw-r--r--llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
index eeaa5ad..c77cc47 100644
--- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
+++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
@@ -1552,7 +1552,8 @@ static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
// fallthrough
default:
Inst.addOperand(MCOperand::createReg(Reg));
- if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
+ if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM ||
+ Inst.getOpcode() == Mips::LWP_MMR6 || Inst.getOpcode() == Mips::SWP_MMR6)
Inst.addOperand(MCOperand::createReg(Reg+1));
Inst.addOperand(MCOperand::createReg(Base));