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| author | Vasileios Kalintiris <Vasileios.Kalintiris@imgtec.com> | 2015-11-06 12:07:20 +0000 |
|---|---|---|
| committer | Vasileios Kalintiris <Vasileios.Kalintiris@imgtec.com> | 2015-11-06 12:07:20 +0000 |
| commit | b04672cadeb424c2ec077b60e176f9499c286a18 (patch) | |
| tree | 42d7dfae747e9929c45013fc7edeb47a3e0355b7 /llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp | |
| parent | 4cd631cd7cc6277c0fe82769099bbaaa4e2948b7 (diff) | |
| download | llvm-b04672cadeb424c2ec077b60e176f9499c286a18.zip llvm-b04672cadeb424c2ec077b60e176f9499c286a18.tar.gz llvm-b04672cadeb424c2ec077b60e176f9499c286a18.tar.bz2 | |
[mips] Define patterns for the atomic_{load,store}_{8,16,32,64} nodes.
Summary:
Without these patterns we would generate a complete LL/SC sequence.
This would be problematic for memory regions marked as WRITE-only or
READ-only, as the instructions LL/SC would read/write to the protected
memory regions correspondingly.
Reviewers: dsanders
Subscribers: llvm-commits, dsanders
Differential Revision: http://reviews.llvm.org/D14397
llvm-svn: 252293
Diffstat (limited to 'llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions