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| author | Simon Dardis <simon.dardis@mips.com> | 2018-05-20 17:21:00 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@mips.com> | 2018-05-20 17:21:00 +0000 |
| commit | 777afc7fbd903f21ba575c800172bca779e264ff (patch) | |
| tree | 80f3a46cdb426466f253498b4e0b96bed3ba7b22 /llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp | |
| parent | a003c728a52a77cf585453313b601edaf5a19225 (diff) | |
| download | llvm-777afc7fbd903f21ba575c800172bca779e264ff.zip llvm-777afc7fbd903f21ba575c800172bca779e264ff.tar.gz llvm-777afc7fbd903f21ba575c800172bca779e264ff.tar.bz2 | |
[mips] Add microMIPSR6 ll/sc instructions.
Previously the compiler was using the microMIPSR3 variants, incorrectly.
Reviewers: atanasyan, abeserminji, smaksimovic
Differential Revision: https://reviews.llvm.org/D46948
llvm-svn: 332820
Diffstat (limited to 'llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index 4cbfca4..eb2c33d 100644 --- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -1860,7 +1860,7 @@ static DecodeStatus DecodeMemMMImm9(MCInst &Inst, Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); Base = getReg(Decoder, Mips::GPR32RegClassID, Base); - if (Inst.getOpcode() == Mips::SCE_MM) + if (Inst.getOpcode() == Mips::SCE_MM || Inst.getOpcode() == Mips::SC_MMR6) Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg)); |