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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-09-14 17:14:57 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-09-14 17:14:57 +0000 |
| commit | 6efd082c01223609117303256dc3a08b143901dd (patch) | |
| tree | 5a229b5b8f3d6be2fe52f12ba07a7d267dd43268 /llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp | |
| parent | a8daf1747c6b93624dac4feed5a9087d8fde0278 (diff) | |
| download | llvm-6efd082c01223609117303256dc3a08b143901dd.zip llvm-6efd082c01223609117303256dc3a08b143901dd.tar.gz llvm-6efd082c01223609117303256dc3a08b143901dd.tar.bz2 | |
AMDGPU: Make frame register caller preserved
Using SplitCSR for the frame register was very broken. Often
the copies in the prolog and epilog were optimized out, in addition
to them being inserted after the true prolog where the FP
was clobbered.
I have a hacky solution which works that continues to use
split CSR, but for now this is simpler and will get to working
programs.
llvm-svn: 313274
Diffstat (limited to 'llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions