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| author | Sagar Thakur <sagar.thakur@imgtec.com> | 2016-05-24 09:57:10 +0000 |
|---|---|---|
| committer | Sagar Thakur <sagar.thakur@imgtec.com> | 2016-05-24 09:57:10 +0000 |
| commit | 672c710de4aaa64a99c8bc08a67f351c1fa932d6 (patch) | |
| tree | 6a1d4b436f348697b4ad3dc58dc649d57b606cf7 /llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp | |
| parent | 6a6185fd78a61eb2a2f05beefe17b67feed86de0 (diff) | |
| download | llvm-672c710de4aaa64a99c8bc08a67f351c1fa932d6.zip llvm-672c710de4aaa64a99c8bc08a67f351c1fa932d6.tar.gz llvm-672c710de4aaa64a99c8bc08a67f351c1fa932d6.tar.bz2 | |
[MIPS][LLVM-MC] Fix Disassemble of Negative Offset
Patch by Nitesh Jain.
Summary: The type of Imm in MipsDisassembler.cpp was incorrect since SignExtend64 return int64_t type.As per the MIPSr6 doc ,the offset is added to the address of the instruction following the branch (not the branch itself), to form a PC-relative effective target address hence “4” is added to the offset. The offset of some test case are update to reflect the changes due to “ + 4 ” offset and new test case for negative offset are added.
Reviewers: dsanders, vkalintiris
Differential Revision: http://reviews.llvm.org/D17540
llvm-svn: 270542
Diffstat (limited to 'llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index 5dfe37f..ad247c3 100644 --- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -580,7 +580,7 @@ static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Rt = fieldFromInstruction(insn, 16, 5); - InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; + int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; bool HasRs = false; if (Rs >= Rt) { @@ -619,7 +619,7 @@ static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Rt = fieldFromInstruction(insn, 16, 5); - InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; + int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; bool HasRs = false; if (Rs >= Rt) { @@ -659,7 +659,7 @@ static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Rt = fieldFromInstruction(insn, 16, 5); - InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; + int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; bool HasRs = false; if (Rt == 0) @@ -704,7 +704,7 @@ static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Rt = fieldFromInstruction(insn, 16, 5); - InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; + int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; if (Rt == 0) return MCDisassembler::Fail; @@ -746,7 +746,7 @@ static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Rt = fieldFromInstruction(insn, 16, 5); - InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; + int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; bool HasRs = false; bool HasRt = false; @@ -795,7 +795,7 @@ static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Rt = fieldFromInstruction(insn, 16, 5); - InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; + int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; bool HasRs = false; if (Rt == 0) @@ -1860,7 +1860,7 @@ static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) { - int32_t BranchOffset = SignExtend32<21>(Offset) * 4; + int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; Inst.addOperand(MCOperand::createImm(BranchOffset)); return MCDisassembler::Success; @@ -1880,7 +1880,7 @@ static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) { - int32_t BranchOffset = SignExtend32<26>(Offset) * 4; + int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4; Inst.addOperand(MCOperand::createImm(BranchOffset)); return MCDisassembler::Success; |