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author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2015-02-10 12:04:41 +0000 |
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committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2015-02-10 12:04:41 +0000 |
commit | 62622d23969b23d44571c67e440053a4dcee6b04 (patch) | |
tree | 81eb2fb5969525de7d2e7e621df3cb76162b3c42 /llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp | |
parent | c4f7fdf57124f1b8dd6c79d901665c55cf7dfa1d (diff) | |
download | llvm-62622d23969b23d44571c67e440053a4dcee6b04.zip llvm-62622d23969b23d44571c67e440053a4dcee6b04.tar.gz llvm-62622d23969b23d44571c67e440053a4dcee6b04.tar.bz2 |
[X86][FastIsel] Avoid introducing legacy SSE instructions if the target has AVX.
This patch teaches X86FastISel how to select AVX instructions for scalar
float/double convert operations.
Before this patch, X86FastISel always selected legacy SSE instructions
for FPExt (from float to double) and FPTrunc (from double to float).
For example:
\code
define double @foo(float %f) {
%conv = fpext float %f to double
ret double %conv
}
\end code
Before (with -mattr=+avx -fast-isel) X86FastIsel selected a CVTSS2SDrr which is
legacy SSE:
cvtss2sd %xmm0, %xmm0
With this patch, X86FastIsel selects a VCVTSS2SDrr instead:
vcvtss2sd %xmm0, %xmm0, %xmm0
Added test fast-isel-fptrunc-fpext.ll to check both the register-register and
the register-memory float/double conversion variants.
Differential Revision: http://reviews.llvm.org/D7438
llvm-svn: 228682
Diffstat (limited to 'llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions