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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-03-01 04:58:17 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-03-01 04:58:17 +0000 |
| commit | 59b8b77405e64c5345ee0f6b98554a17a0e5f81e (patch) | |
| tree | bb78f980d6d29bf1fb182fc4548c667a358e0778 /llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp | |
| parent | 14a79d7736e9d55f8782fee822921aae8330ea16 (diff) | |
| download | llvm-59b8b77405e64c5345ee0f6b98554a17a0e5f81e.zip llvm-59b8b77405e64c5345ee0f6b98554a17a0e5f81e.tar.gz llvm-59b8b77405e64c5345ee0f6b98554a17a0e5f81e.tar.bz2 | |
AMDGPU: Set HasExtractBitInsn
This currently does not have the control over the bitwidth,
and there are missing optimizations to reduce the integer to
32-bit if it can be.
But in most situations we do want the sinking to occur.
llvm-svn: 262296
Diffstat (limited to 'llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions