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| author | Simon Dardis <simon.dardis@imgtec.com> | 2016-06-14 11:29:28 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@imgtec.com> | 2016-06-14 11:29:28 +0000 |
| commit | 4fbf76f7c34b1c7242340d79a0c256b0e5293346 (patch) | |
| tree | 9e0b2f2281d4d38e81796b4dd72c1eb4e145318b /llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp | |
| parent | 6465008e0e36f5d592999783b569b5c0c43a680c (diff) | |
| download | llvm-4fbf76f7c34b1c7242340d79a0c256b0e5293346.zip llvm-4fbf76f7c34b1c7242340d79a0c256b0e5293346.tar.gz llvm-4fbf76f7c34b1c7242340d79a0c256b0e5293346.tar.bz2 | |
[mips][atomics] Fix atomic instruction descriptions and uses.
PR27458 highlights that the MIPS backend does not have well formed
MIR for atomic operations (among other errors).
This patch adds expands and corrects the LL/SC descriptions and uses
for MIPS(64).
Reviewers: dsanders, vkalintiris
Differential Review: http://reviews.llvm.org/D19719
llvm-svn: 272655
Diffstat (limited to 'llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index f5fc090..9124d87 100644 --- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -39,6 +39,7 @@ public: IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), IsBigEndian(IsBigEndian) {} + bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; } bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } bool hasMips32r6() const { @@ -48,6 +49,8 @@ public: bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } + bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; } + bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } bool hasCOP3() const { @@ -1049,6 +1052,16 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, } } + if (hasMips32r6() && isPTR64()) { + DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn, + Address, this, STI); + if (Result != MCDisassembler::Fail) { + Size = 4; + return Result; + } + } + if (hasMips32r6()) { DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, @@ -1059,6 +1072,16 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, } } + if (hasMips2() && isPTR64()) { + DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn, + Address, this, STI); + if (Result != MCDisassembler::Fail) { + Size = 4; + return Result; + } + } + if (hasCnMips()) { DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, |