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author | Petar Jovanovic <petar.jovanovic@mips.com> | 2018-03-14 14:13:31 +0000 |
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committer | Petar Jovanovic <petar.jovanovic@mips.com> | 2018-03-14 14:13:31 +0000 |
commit | 3408caf68662ff8df209e52ab3aa4e27c14a371d (patch) | |
tree | 0fdff253a660258d80f592b83bbcb99343ffc49f /llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp | |
parent | d5949429280b625d8d77becdb47fbd75bc8a4e0f (diff) | |
download | llvm-3408caf68662ff8df209e52ab3aa4e27c14a371d.zip llvm-3408caf68662ff8df209e52ab3aa4e27c14a371d.tar.gz llvm-3408caf68662ff8df209e52ab3aa4e27c14a371d.tar.bz2 |
[mips] Add support for CRC ASE
This includes
Instructions: crc32b, crc32h, crc32w, crc32d,
crc32cb, crc32ch, crc32cw, crc32cd
Assembler directives: .set crc, .set nocrc, .module crc, .module nocrc
Attribute: crc
.MIPS.abiflags: CRC (0x8000)
Patch by Vladimir Stefanovic.
Differential Revision: https://reviews.llvm.org/D44176
llvm-svn: 327511
Diffstat (limited to 'llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp')
-rw-r--r-- | llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index 3d29a0d..2f9c286 100644 --- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -517,6 +517,10 @@ template <typename InsnType> static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder); +template <typename InsnType> +static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); @@ -1129,6 +1133,22 @@ static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, return MCDisassembler::Success; } + +// Auto-generated decoder wouldn't add the third operand for CRC32*. +template <typename InsnType> +static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, + const void *Decoder) { + InsnType Rs = fieldFromInstruction(Insn, 21, 5); + InsnType Rt = fieldFromInstruction(Insn, 16, 5); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, + Rt))); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, + Rs))); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, + Rt))); + return MCDisassembler::Success; +} + /// Read two bytes from the ArrayRef and return 16 bit halfword sorted /// according to the given endianness. static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, |